Dmitry Shalnoff's Git Repository - AXOD IR_433MHz Shield/blob - HARDWARE/RF_RX.kicad_pro

   1 {
   2   "board": {
   3     "3dviewports": [],
   4     "design_settings": {
   5       "defaults": {
   6         "board_outline_line_width": 0.09999999999999999,
   7         "copper_line_width": 0.19999999999999998,
   8         "copper_text_italic": false,
   9         "copper_text_size_h": 1.5,
  10         "copper_text_size_v": 1.5,
  11         "copper_text_thickness": 0.3,
  12         "copper_text_upright": false,
  13         "courtyard_line_width": 0.049999999999999996,
  14         "dimension_precision": 4,
  15         "dimension_units": 3,
  16         "dimensions": {
  17           "arrow_length": 1270000,
  18           "extension_offset": 500000,
  19           "keep_text_aligned": true,
  20           "suppress_zeroes": false,
  21           "text_position": 0,
  22           "units_format": 1
  23         },
  24         "fab_line_width": 0.09999999999999999,
  25         "fab_text_italic": false,
  26         "fab_text_size_h": 1.0,
  27         "fab_text_size_v": 1.0,
  28         "fab_text_thickness": 0.15,
  29         "fab_text_upright": false,
  30         "other_line_width": 0.15,
  31         "other_text_italic": false,
  32         "other_text_size_h": 1.0,
  33         "other_text_size_v": 1.0,
  34         "other_text_thickness": 0.15,
  35         "other_text_upright": false,
  36         "pads": {
  37           "drill": 2.75,
  38           "height": 2.75,
  39           "width": 2.75
  40         },
  41         "silk_line_width": 0.15,
  42         "silk_text_italic": false,
  43         "silk_text_size_h": 1.0,
  44         "silk_text_size_v": 1.0,
  45         "silk_text_thickness": 0.15,
  46         "silk_text_upright": false,
  47         "zones": {
  48           "min_clearance": 0.0
  49         }
  50       },
  51       "diff_pair_dimensions": [],
  52       "drc_exclusions": [],
  53       "meta": {
  54         "version": 2
  55       },
  56       "rule_severities": {
  57         "annular_width": "error",
  58         "clearance": "error",
  59         "connection_width": "warning",
  60         "copper_edge_clearance": "error",
  61         "copper_sliver": "warning",
  62         "courtyards_overlap": "error",
  63         "diff_pair_gap_out_of_range": "error",
  64         "diff_pair_uncoupled_length_too_long": "error",
  65         "drill_out_of_range": "error",
  66         "duplicate_footprints": "warning",
  67         "extra_footprint": "warning",
  68         "footprint": "error",
  69         "footprint_type_mismatch": "ignore",
  70         "hole_clearance": "error",
  71         "hole_near_hole": "error",
  72         "invalid_outline": "error",
  73         "isolated_copper": "warning",
  74         "item_on_disabled_layer": "error",
  75         "items_not_allowed": "error",
  76         "length_out_of_range": "error",
  77         "lib_footprint_issues": "warning",
  78         "lib_footprint_mismatch": "warning",
  79         "malformed_courtyard": "error",
  80         "microvia_drill_out_of_range": "error",
  81         "missing_courtyard": "ignore",
  82         "missing_footprint": "warning",
  83         "net_conflict": "warning",
  84         "npth_inside_courtyard": "ignore",
  85         "padstack": "warning",
  86         "pth_inside_courtyard": "ignore",
  87         "shorting_items": "error",
  88         "silk_edge_clearance": "warning",
  89         "silk_over_copper": "warning",
  90         "silk_overlap": "warning",
  91         "skew_out_of_range": "error",
  92         "solder_mask_bridge": "error",
  93         "starved_thermal": "error",
  94         "text_height": "warning",
  95         "text_thickness": "warning",
  96         "through_hole_pad_without_hole": "error",
  97         "too_many_vias": "error",
  98         "track_dangling": "warning",
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 100         "tracks_crossing": "error",
 101         "unconnected_items": "error",
 102         "unresolved_variable": "error",
 103         "via_dangling": "warning",
 104         "zones_intersect": "error"
 105       },
 106       "rules": {
 107         "max_error": 0.005,
 108         "min_clearance": 0.0,
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 112         "min_hole_to_hole": 0.25,
 113         "min_microvia_diameter": 0.19999999999999998,
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 115         "min_resolved_spokes": 2,
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 122         "min_via_diameter": 0.5,
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 124         "solder_mask_min_width": 0.0,
 125         "solder_mask_to_copper_clearance": 0.0,
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 127       },
 128       "teardrop_options": [
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 130           "td_allow_use_two_tracks": true,
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 134           "td_onroundshapesonly": false,
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 137         }
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 166         }
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 172     "layer_presets": [],
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 175   "boards": [],
 176   "cvpcb": {
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 354     "rule_severities": {
 355       "bus_definition_conflict": "error",
 356       "bus_entry_needed": "error",
 357       "bus_to_bus_conflict": "error",
 358       "bus_to_net_conflict": "error",
 359       "conflicting_netclasses": "error",
 360       "different_unit_footprint": "error",
 361       "different_unit_net": "error",
 362       "duplicate_reference": "error",
 363       "duplicate_sheet_names": "error",
 364       "endpoint_off_grid": "warning",
 365       "extra_units": "error",
 366       "global_label_dangling": "warning",
 367       "hier_label_mismatch": "error",
 368       "label_dangling": "error",
 369       "lib_symbol_issues": "warning",
 370       "missing_bidi_pin": "warning",
 371       "missing_input_pin": "warning",
 372       "missing_power_pin": "error",
 373       "missing_unit": "warning",
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 382       "similar_labels": "warning",
 383       "simulation_model_issue": "ignore",
 384       "unannotated": "error",
 385       "unit_value_mismatch": "error",
 386       "unresolved_variable": "error",
 387       "wire_dangling": "error"
 388     }
 389   },
 390   "libraries": {
 391     "pinned_footprint_libs": [],
 392     "pinned_symbol_libs": []
 393   },
 394   "meta": {
 395     "filename": "RF_RX.kicad_pro",
 396     "version": 1
 397   },
 398   "net_settings": {
 399     "classes": [
 400       {
 401         "bus_width": 12,
 402         "clearance": 0.2,
 403         "diff_pair_gap": 0.25,
 404         "diff_pair_via_gap": 0.25,
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 408         "microvia_drill": 0.1,
 409         "name": "Default",
 410         "pcb_color": "rgba(0, 0, 0, 0.000)",
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 414         "via_drill": 0.4,
 415         "wire_width": 6
 416       }
 417     ],
 418     "meta": {
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 420     },
 421     "net_colors": null,
 422     "netclass_assignments": null,
 423     "netclass_patterns": []
 424   },
 425   "pcbnew": {
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 463     "spice_external_command": "spice \"%I\"",
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 465     "spice_save_all_currents": false,
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 476   "text_variables": {}
 477 }